MC908AP8CFBE Datasheet, PDF(118/324 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC908AP8CFBE Datasheet, PDF (118/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Table 8-1. Monitor Mode Signal Requirements and Options

IRQ1

RST

Address

$FFFE/

$FFFF

PTA2

PTA1

PTA0

(1)

PTB0

External

Clock(2)

Bus

Frequency

PLL

COP

Baud

Rate

Comment

X GND

X

X

X

X

X

X

0

X Disabled

0

No operation until

reset goes high

VDD

VTST(3)

or

X

VTST

PTA1 and PTA2

voltages only

0

1

1

0

4.9152

MHz

2.4576

MHz

OFF Disabled

9600

required if

IRQ1 = VTST;

PTB0 determines

frequency divider

VDD

VTST(3)

or

X

VTST

PTA1 and PTA2

voltages only

0

1

1

1

9.8304

MHz

2.4576

MHz

OFF Disabled

9600

required if

IRQ1 = VTST;

PTB0 determines

frequency divider

VDD

VDD

Blank

"$FFFF"

X

X

1

X

9.8304

MHz

2.4576

MHz

OFF Disabled

9600

External frequency

always divided by 4

GND

VDD

Blank

"$FFFF"

X

X

1

X

32.768

kHz

2.4576

MHz

ON Disabled

9600

PLL enabled

(BCS set)

in monitor mode

VDD

or

VTST

Blank

"$FFFF"

X

X

X

X

X

GND

Enters user

â

OFF Enabled

â

mode â will

encounter an illegal

address reset

VDD

VDD

or

or Not Blank X

X

X

X

X

GND VTST

â

OFF Enabled

â Enters user mode

1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication

2. External clock is derived by a 32.768kHz crystal or a 4.9152/9.8304MHz off-chip oscillator.

3. Monitor mode entry by IRQ1= VTST, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is by-

passed.

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