MC68HC908GR16A Datasheet, PDF (66/270 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Clock Generator Module (CGM)
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at start up.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL) — See 4.5.1 PLL Control Register
• PLL bandwidth control register (PBWC) — see 4.5.2 PLL Bandwidth Control Register
• PLL multiplier select register high (PMSH) — see 4.5.3 PLL Multiplier Select Register High
• PLL multiplier select register low (PMSL) — see 4.5.4 PLL Multiplier Select Register Low
• PLL VCO range select register (PMRS) — see 4.5.5 PLL VCO Range Select Register
Figure 4-3 is a summary of the CGM registers.
Addr.
Register Name
Bit 7
6
5
$0036
PLL Control Register Read:
(PCTL) Write:
PLLIE
PLLF
PLLON
See page 67. Reset: 0
0
1
$0037
PLL Bandwidth Control Read:
Register (PBWC) Write:
AUTO
LOCK
ACQ
See page 68. Reset: 0
0
0
PLL Multiplier Select High Read: 0
0
0
$0038
Register (PMSH) Write:
See page 69. Reset: 0
0
0
$0039
PLL Multiplier Select Low Read:
Register (PMSL) Write:
MUL7
MUL6
MUL5
See page 70. Reset: 0
1
0
$003A
PLL VCO Select Range Read:
Register (PMRS) Write:
VRS7
VRS6
VRS5
See page 70. Reset: 0
1
0
Read: 0
0
0
$003B
Reserved Register Write:
Reset: 0
0
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
4
3
BCS
R
0
0
0
0
0
0
0
MUL4
0
VRS4
0
0
0
R
0
MUL11
0
MUL3
0
VRS3
0
R
0
= Reserved
Figure 4-3. CGM I/O Register Summary
2
R
0
0
0
MUL10
0
MUL2
0
VRS2
0
R
0
1
VPR1
0
0
0
MUL9
0
MUL1
0
VRS1
0
R
0
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
R
1
MC68HC908GR16A Data Sheet, Rev. 1.0
66
Freescale Semiconductor