MC68HC908GR16A Datasheet, PDF (146/270 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
The baud rate clock source for the ESCI can be selected via the configuration bit, ESCIBDSRC, of the
CONFIG2 register ($001E).
For reference, a summary of the ESCI module input/output registers is provided in Figure 14-3.
Addr.
$0009
$000A
$000B
$0013
$0014
$0015
$0016
$0017
$0018
$0019
Register Name
Bit 7
6
5
4
3
2
1
ESCI Prescaler Register ^Read:
(SCPSC) Write:
See page 166. _Reset:
PDS2
0
PDS1
0
PDS0
0
PSSB4
0
PSSB3
0
PSSB2
0
PSSB1
0
ESCI Arbiter Control ^Read: _AM1
ALOST
AM0
Register (SCIACTL) Write:
See page 170. _Reset:
0
0
0
ACLK
0
AFIN
ARUN AROVFL
0
0
0
ESCI Arbiter Data ^Read:
Register (SCIADAT) Write:
See page 171. _Reset:
ARD7
0
ARD6
0
ARD5
0
ARD4
0
ARD3
0
ARD2
0
ARD1
0
ESCI Control Register 1 ^Read: _{LOOPS ENSCI}
TXINV
M
WAKE
ILTY
PEN
(SCC1) Write:
See page 157. _Reset:
0
0
0
0
0
0
0
ESCI Control Register 2 ^Read: _SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
(SCC2) Write:
See page 159. _Reset:
0
0
0
0
0
0
0
ESCI Control Register 3 ^{Read: R8}
T8
R
(SCC3) Write:
See page 160. _{Reset: U}
0
0
R
ORIE
NEIE
FEIE
0
0
0
0
ESCI Status Register 1 ^{Read: SCTE}
TC
SCRF
IDLE
OR
NF
FE
(SCS1) Write:
See page 161. _Reset:
1
1
0
0
0
0
0
ESCI Status Register 2 ^Read:
0
0
0
0
0
0
BKF
(SCS2) Write:
See page 164. _Reset:
0
0
0
0
0
0
0
ESCI Data Register ^{Read: R7}
R6
R5
R4
R3
R2
R1
(SCDR) Write: T7
T6
T5
T4
T3
T2
T1
See page 164. _Reset:
Unaffected by reset
ESCI Baud Rate Register ^Read: _LINT
LINR
SCP1
SCP0
R
SCR2
SCR1
(SCBR) Write:
See page 165. _Reset:
0
0
0
0
0
0
0
= Unimplemented
R = Reserved U = Unaffected
Figure 14-3. ESCI I/O Register Summary
Bit 0
PSSB0
0
ARD8
0
ARD0
0
PTY
0
SBK
0
PEIE
0
PE
0
RPF
0
R0
T0
SCR0
0
MC68HC908GR16A Data Sheet, Rev. 1.0
146
Freescale Semiconductor