MC68HC908GR16A Datasheet, PDF (181/270 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Exception Control
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See Figure 15-10.
FROM RESET
I BBIRTESAEKT?
YES
INTERRUPT?
NO
YES
I BIT SET?
NO
IRQ
YES
INTERRUPT?
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
YES
INSTRUCTION?
NO
RTI
YES
INSTRUCTION?
NO
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 15-10. Interrupt Processing
MC68HC908GR16A Data Sheet, Rev. 1.0
Freescale Semiconductor
181