MC68HC908GR16A Datasheet, PDF (167/270 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

I/O Registers
PDS2–PDS0 — Prescaler Divisor Select Bits
These read/write bits select the prescaler divisor as shown in Table 14-10. Reset clears PDS2–PDS0.
NOTE
The setting of ‘000’ will bypass not only this prescaler but also the prescaler
divisor fine adjust (PDFA). It is not recommended to bypass the prescaler
while ENSCI is set, because the switching is not glitch free.
Table 14-10. ESCI Prescaler Division Ratio
PS[2:1:0]
000
001
010
011
100
101
110
111
Prescaler Divisor (PD)
Bypass this prescaler
2
3
4
5
6
7
8
PSSB4–PSSB0 — Clock Insertion Select Bits
These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average prescaler frequency as shown in Table 14-11. Reset clears
PSSB4–PSSB0.
Table 14-11. ESCI Prescaler Divisor Fine Adjust
PSSB[4:3:2:1:0]
Prescaler Divisor Fine Adjust (PDFA)
00000
0/32 = 0
00001
00010
1/32 = 0.03125
2/32 = 0.0625
00011
3/32 = 0.09375
00100
4/32 = 0.125
00101
00110
00111
5/32 = 0.15625
6/32 = 0.1875
7/32 = 0.21875
01000
8/32 = 0.25
01001
9/32 = 0.28125
01010
01011
10/32 = 0.3125
11/32 = 0.34375
01100
12/32 = 0.375
01101
13/32 = 0.40625
01110
01111
14/32 = 0.4375
15/32 = 0.46875
Continued on next page
MC68HC908GR16A Data Sheet, Rev. 1.0
Freescale Semiconductor
167