MC68HC908GR16A Datasheet, PDF (165/270 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

I/O Registers
14.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
NOTE
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Address:
Read:
Write:
Reset:
$0019
Bit 7
6
5
4
3
2
1
LINT
LINR
SCP1
SCP0
R
SCR2
SCR1
0
0
0
0
0
0
0
R
= Reserved
Figure 14-17. ESCI Baud Rate Register (SCBR)
Bit 0
SCR0
0
LINT — LIN Break Symbol Transmit Enable
This read/write bit selects the enhanced ESCI features for master nodes in the local interconnect
network (LIN) protocol (version 1.2) as shown in Table 14-6. Reset clears LINT.
Table 14-6. ESCI LIN Master Node Control Bits
LINT
0
1
1
M
Functionality
X Normal ESCI functionality
0 13-bit break generation enabled for LIN transmitter
1 14-bit break generation enabled for LIN transmitter
NOTE
LIN master nodes require significantly tighter timing tolerances than slave
nodes. Be sure to consult the current LIN specification to ensure that timing
requirements are met properly. Generally, these timing tolerances require
crystals or oscillators to be used, rather than internal clocking circuits.
LINR — LIN Break Symbol Receiver Bits
This read/write bit selects the enhanced ESCI features for slave nodes in the local interconnect
network (LIN) protocol as shown in Table 14-7. Reset clears LINR.
Table 14-7. ESCI LIN Slave Node Control Bits
LINR
0
1
1
M
Functionality
X Normal ESCI functionality
0 11-bit break detect enabled for LIN receiver
1 12-bit break detect enabled for LIN receiver
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
MC68HC908GR16A Data Sheet, Rev. 1.0
Freescale Semiconductor
165