MC68HC908GR16A Datasheet, PDF (242/270 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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Table 19-2. Mode Differences
Modes
User
Monitor
Reset
Vector High
$FFFE
$FEFE
Reset
Vector Low
$FFFF
$FEFF
Functions
Break
Break
Vector High Vector Low
$FFFC
$FFFD
$FEFC
$FEFD
SWI
Vector High
$FFFC
$FEFC
SWI
Vector Low
$FFFD
$FEFD
19.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
START
BIT BIT 0
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
NEXT
START
BIT 6 BIT 7 STOP BIT
BIT
Figure 19-12. Monitor Data Format
19.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of approximately two bits and then echoes back the break signal.
MISSING STOP BIT
APPROXIMATELY 2 BITS DELAY
BEFORE ZERO ECHO
01234567
01234567
Figure 19-13. Break Transaction
19.3.1.6 Baud Rate
The communication baud rate is controlled by the crystal frequency or external clock and the state of the
PTB4 pin (when IRQ is set to V_TST) upon entry into monitor mode. If monitor mode was entered with V_DD
on IRQ and the reset vector blank, then the baud rate is independent of PTB4.
Table 19-1 also lists external frequencies required to achieve a standard baud rate of 7200 bps. The
effective baud rate is the bus frequency divided by 278. If using a crystal as the clock source, be aware
of the upper frequency limit that the internal clock module can handle. See 20.5 5-Vdc Electrical
Characteristics or 20.6 3.3-Vdc Electrical Characteristics for this limit.
19.3.1.7 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
MC68HC908GR16A Data Sheet, Rev. 1.0
242
Freescale Semiconductor