K60P100M100SF2 Datasheet, PDF (66/73 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Pinout
8.1 K60 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
The 81-pin ballmap assignments are currently being developed.
The • in the entries in this package column indicate which
signals are present on the package.
100 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQF
P
1 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1
I2C1_SDA
2 PTE1
ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT UART1_RX SDHC0_D0
I2C1_SCL
3 PTE2
ADC1_SE6a ADC1_SE6a PTE2
SPI1_SCK UART1_CTS SDHC0_DCL
_b
K
4 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN UART1_RTS SDHC0_CM
_b
D
5 PTE4
DISABLED
PTE4
SPI1_PCS0 UART3_TX SDHC0_D3
6 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
7 PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CTS I2S0_MCLK
_b
I2S0_CLKIN
8 VDD
VDD
VDD
9 VSS
VSS
VSS
10 USB0_DP USB0_DP USB0_DP
11 USB0_DM USB0_DM USB0_DM
12 VOUT33 VOUT33 VOUT33
13 VREGIN VREGIN VREGIN
14 ADC0_DP1 ADC0_DP1 ADC0_DP1
15 ADC0_DM1 ADC0_DM1 ADC0_DM1
16 ADC1_DP1 ADC1_DP1 ADC1_DP1
17 ADC1_DM1 ADC1_DM1 ADC1_DM1
18 PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
19 PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
20 PGA1_DP/ PGA1_DP/ PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
21 PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
22 VDDA
VDDA
VDDA
23 VREFH
VREFH
VREFH
EzPort
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
66
Preliminary
Freescale Semiconductor, Inc.