K60P100M100SF2 Datasheet, PDF (59/73 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Num
DS9
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Peripheral operating requirements and behaviors
Table 40. Slave mode DSPI timing (low-speed mode)
Operating voltage
Description
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Min.
1.71
—
8 x t_BCLK
(t_SCK/2) - 4
—
0
5
15
—
—
Max.
3.6
6.25
—
(t_SCK/2) + 4
20
—
—
—
15
15
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
DS11
Last data
DS16
Last data
Figure 25. DSPI classic SPI timing — slave mode
6.8.7 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 41. Master mode DSPI timing (high-speed mode)
Num
Description
Operating voltage
Frequency of operation
Min.
2.7
—
Max.
3.6
25
Unit
V
MHz
Table continues on the next page...
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
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