K60P100M100SF2 Datasheet, PDF (36/73 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications
Num
EP1
EP1a
Description
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
Min.
2.7
—
—
EP2
EZP_CS negation to next EZP_CS assertion
EP3
EZP_CS input valid to EZP_CK high (setup)
EP4
EZP_CK high to EZP_CS input invalid (hold)
EP5
EZP_D input valid to EZP_CK high (setup)
EP6
EZP_CK high to EZP_D input invalid (hold)
EP7
EZP_CK low to EZP_Q output valid (setup)
EP8
EZP_CK low to EZP_Q output invalid (hold)
EP9
EZP_CS negation to EZP_Q tri-state
2 x t_{EZP_CK}
5
5
2
5
—
0
—
Max.
3.6
f_SYS/2
f_SYS/8
—
—
—
—
—
12
—
12
Unit
V
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
EP7
EP8
EP5
EP6
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
36
Preliminary
Freescale Semiconductor, Inc.