MC68HC08JL8 Datasheet, PDF (61/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5
System Integration Module (SIM)
5.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM
is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state
controller that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 5-1 shows the internal signal names used in this section.
Table 5-1. Signal Name Conventions
Signal Name
ICLK
OSCOUT
IAB
IDB
PORRST
IRST
R/W
Description
Internal oscillator clock
The XTAL or RC frequency divided by two. This signal is again divided by two in the SIM
to generate the internal bus clocks. (Bus clock = OSCOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
Freescale Semiconductor
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