MC68HC08JL8 Datasheet, PDF (148/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
10.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before attempting a new ADC conversion after exiting stop mode.
10.6 I/O Signals
The ADC module has 12 channels that are shared with I/O port B and port D, and one channel on
ADC12/T2CLK pin.
10.6.1 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the 13 ADC channels to the ADC module.
10.7 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
10.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register.
Address: $003C
Bit 7
6
5
4
3
2
1
Read: COCO
AIEN
ADCO ADCH4 ADCH3 ADCH2 ADCH1
Write:
Reset: 0
0
0
1
1
1
1
= Unimplemented
Figure 10-3. ADC Status and Control Register (ADSCR)
Bit 0
ADCH0
1
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed. This bit is cleared whenever the ADC status and control register is written or whenever the
ADC data register is read. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always
be logic 0 when read.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
148
Freescale Semiconductor