MC68HC08JL8 Datasheet, PDF (154/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
Address:
Read:
Write:
Reset:
$0004
Bit 7
6
5
4
3
2
1
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1
0
0
0
0
0
0
0
Figure 11-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 11-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAPUEx
PTAx
READ PTA ($0000)
To KBI
Figure 11-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 11-2 summarizes the operation of the port A pins.
Table 11-2. Port A Pin Functions
PTAPUE
Bit
DDRA Bit
1
0
0
0
X
1
PTA Bit
X⁽¹⁾
X
X
I/O Pin Mode
Input, V_DD(2)
Input, Hi-Z⁽⁴⁾
Output
Accesses to DDRA
Read/Write
DDRA[7:0]
DDRA[7:0]
DDRA[7:0]
1. X = Don’t care.
2. Pin pulled to V_DD by internal pull-up.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance.
Accesses to PTA
Read
Write
Pin
PTA[7:0]⁽³⁾
Pin
PTA[7:0]⁽³⁾
PTA[7:0] PTA[7:0]
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
154
Freescale Semiconductor