MC68HC08JL8 Datasheet, PDF (161/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port E
T2CH1, T2CH0 — Timer 2 Channel I/Os
The T2CH1 and T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTE0/T2CH0 and PTE1/T2CH1 pins are timer channel I/O
pins or general-purpose I/O pins. See Chapter 8 Timer Interface Module (TIM).
11.5.2 Data Direction Register E (DDRE)
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
NOTE
For those devices packaged in a 20-pin package and 28-pin package, PTE0–PTE1 are not connected.
DDRE0–DDRE1 should be set to a 1 to configure PTE0–PTE1 as outputs.
Address:
Read:
Write:
Reset:
$000C
Bit 7
6
5
4
3
2
1
DDRE1
0
0
0
0
0
0
0
Figure 11-15. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
DDRE[1:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[1:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1. Figure 11-16 shows the
port E I/O logic.
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
WRITE PTE ($0008)
DDREx
PTEx
PTEx
READ PTE ($0008)
Figure 11-16. Port E I/O Circuit
To TIM2
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
Freescale Semiconductor
161