MC68HC08JL8 Datasheet, PDF(190/212 Page) Freescale Semiconductor, Inc

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MC68HC08JL8 Datasheet, PDF (190/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Electrical Specifications

Table 17-7. DC Electrical Characteristics (3V)

Characteristic(1)

Capacitance

Ports (as input or output)

POR rearm voltage(6)

POR rise time ramp rate(7)

Monitor mode entry voltage

Pullup resistors(8)

PTD6, PTD7

RST, IRQ, PTA0âPTA7

Low-voltage inhibit, trip voltage

(No hysteresis implemented for 3V LVI)

Symbol

COUT

CIN

VPOR

RPOR

VTST

RPU1

RPU2

VLVI3

Min

0.035

1.5 Ã VDD

1.8

2.18

Typ(2)

3.3

2.49

Max

100

8.5

4.8

2.68

Unit

V/ms

kâ¦

1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25 Â°C only.

3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads.

Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects

run IDD. Measured with all modules enabled.

4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than

100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.

5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.

6. Maximum is highest voltage that POR is guaranteed.

7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum

VDD is reached.

8. RPU1 and RPU2 are measured at VDD = 5.0V.

17.9 3V Control Timing

Table 17-8. Control Timing (3V)

Characteristic(1)

Symbol

Min

Max

Unit

Internal operating frequency

RST input pulse width low(2)

TIM2 external clock input

IRQ interrupt pulse width low (edge-triggered)(3)

IRQ interrupt pulse period(3)

fOP

MHz

tRL

1.5

Âµs

fT2CLK

MHz

tILIH

200

tILIL

Note(4)

tCYC

1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise

noted.

2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.

3. Values are based on characterization results, not tested in production.

4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.

tRL

RST

tILIL

tILIH

IRQ

Figure 17-3. RST and IRQ Timing

MC68HC908JL8/JK8 â¢ MC68HC08JL8/JK8 â¢ MC68HC908KL8 Data Sheet, Rev. 3.1

190

Freescale Semiconductor

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