MC68HC08JL8 Datasheet, PDF (30/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory
Addr.
$0035
$0036
$0037
$0038
$0039
$003A
$003B
Register Name
TIM2 Channel 0 Status ^Read:
and Control Register Write:
(T2SC0) Reset:
TIM2 Channel 0 ^Read:
Register High Write:
(T2CH0H) Reset:
TIM2 Channel 0 ^Read:
Register Low Write:
(T2CH0L) Reset:
TIM2 Channel 1 Status ^Read:
and Control Register Write:
(T2SC1) Reset:
TIM2 Channel 1 ^Read:
Register High Write:
(T2CH1H) Reset:
TIM2 Channel 1 ^Read:
Register Low Write:
(T2CH1L) Reset:
Read:
Unimplemented Write:
Bit 7
CH0F
0
0
Bit15
Bit7
CH1F
0
0
Bit15
Bit7
6
CH0IE
0
Bit14
Bit6
CH1IE
0
Bit14
Bit6
5
4
3
2
MS0B MS0A ELS0B ELS0A
0
0
0
0
Bit13 Bit12 Bit11 Bit10
Indeterminate after reset
Bit5
Bit4
Bit3
Bit2
Indeterminate after reset
0
MS1A ELS1B ELS1A
0
0
0
0
Bit13 Bit12 Bit11 Bit10
Indeterminate after reset
Bit5
Bit4
Bit3
Bit2
Indeterminate after reset
1
TOV0
0
Bit9
Bit 0
CH0MAX
0
Bit8
Bit1
Bit0
TOV1
0
Bit9
CH1MAX
0
Bit8
Bit1
Bit0
$003C
$003D
$003E
$003F
ADC Status and Control ^Read:
Register Write:
(ADSCR) _Reset:
Read:
ADC Data Register
(ADR)
Write:
Reset:
Read:
ADC Input Clock Register
(ADICLK)
Write:
Reset:
Read:
Unimplemented Write:
COCO
0
AD7
ADIV2
0
AIEN
0
AD6
ADIV1
0
ADCO
0
AD5
ADCH4
1
AD4
ADCH3
1
AD3
ADCH2
1
AD2
ADCH1
1
AD1
ADCH0
1
AD0
Indeterminate after reset
ADIV0
0
0
0
0
0
0
0
0
0
0
0
Read:
SBSW
$FE00 Break Status Register (BSR) Write:
R
R
R
R
R
R
See note
R
Reset:
0
Note: Writing a logic 0 clears SBSW.
Read: POR
PIN
COP
ILOP
ILAD MODRST LVI
0
$FE01 Reset Status Register (RSR) Write:
POR: 1
0
0
0
0
0
0
0
$FE02
Read:
Reserved Write:
R
R
R
R
R
R
R
R
Break Flag Control ^Read:
$FE03
Register Write:
(BFCR) Reset:
U = Unaffected
BCFE
R
0
X = Indeterminate
R
R
R
= Unimplemented
R
R
R
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
30
Freescale Semiconductor