MCF5272VF66J Datasheet, PDF(536/544 Page) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

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MCF5272VF66J Datasheet, PDF (536/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

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Index

interrupt controller, pending and mask, 7-4, 7-5

JTAG instruction, 21-7

local memory, 4-2

MASK, 2-6

maximum frame length, 11-24

MBAR, 2-9, 6-3

MII management frame, 11-17

MII speed control, 11-18

module base address, 2-9

output port command, 16-18

P0B1RRâP3B1RR, 13-15

P0B2RRâP3B2RR, 13-16

P0CRâP3CR, 13-18

P0GCIRâP3GCIR, 13-28

P0GMTâP3GMT, 13-25

P0ICRâP3ICR, 13-20

P0PSRâP3PSR, 13-22

P0SDRâP3SDR, 13-33

P3B1TRâP0B1TR, 13-17

P3B2TRâP0B2TR, 13-17

P3DRRâP0DRR, 13-16

P3DTRâP0DTR, 13-18

P3GCITâP0GCIT, 13-29

P3GMRâP0GMR, 13-24

PADDR, 17-10

PAR, 7-9

PASR, 13-23

PBDDR, 17-10

PBR, 5-13

PCDDR, 17-11

PCSR, 13-34

PDCSR, 13-31

PDRQR, 13-32

PGCITSR, 13-30

PGMTA, 13-26

PGMTS, 13-27

PLCR, 13-20

PLIC

aperiodic status, 13-23

B1 data transmit, 13-17

B2 data receive, 13-16

clock select, 13-34

D data transmit, 13-18

D-Channel status, 13-31

GCI C/I channel

receive, 13-28

transmit, 13-29

GCI monitor channel

general, 13-24

transmit, 13-25

transmit status, 13-27

general, 13-15

interrupt configuration, 13-20

loopback control, 13-20

memory map, 13-13

periodic status, 13-22

port configuration, 13-18

receive data, 13-3

sync delay, 13-33

transmit data, 13-4

PMR, 6-7

pointer-to-receive descriptor ring, 11-30

pointer-to-transmit descriptor ring, 11-31

power management, 6-7

PWM control, 18-3

PWM width, 18-4

QSPI

address, 14-14

data, 14-14

delay, 14-11

interrupt, 14-13

mode, 14-9

wrap, 14-12

RAM base address, 2-9

RAM perfect match address

high, 11-27

low, 11-26

RAMBAR, 2-9

RAREG/RDREG, 5-22

RCREG, 5-30

RDMREG, 5-32

read control, 5-30

read debug module, 5-32

receive buffer size, 11-32

receive control, 11-23

ROM base address, 4-5

SCR, 6-5

SDCR, 9-6

SDRAM

configuration, 9-6

general, 9-6

timing, 9-8

SDTR, 9-8

SIM

base address, 7-6, 7-8

memory map, 6-2

module base address, 6-3

SPR, 6-6

SR, 2-8

SRAM base address, 4-3

status, 2-8, 2-8

system configuration, 6-5

system protection, 6-6

TCR, 15-4

TDR, 5-14

TER, 15-5

timer

capture, 15-4

event, 15-5

general-purpose, 15-3

Index-6

MCF5272 ColdFireÂ® Integrated Microprocessor Userâs Manual, Rev. 3

Freescale Semiconductor

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