MCF5272VF66J Datasheet, PDF (173/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

System Integration Module (SIM)
Table 6-10. WIRR Field Descriptions
Bits Field
Description
15-1 REF Reference value. Contains the reference value for the watchdog timeout causing an interrupt.
0 IEN Enable interrupt. When enabled, software should periodically write to WCR to avoid reaching the interrupt
reference value.
0 Disable interrupt.
1 Enable interrupt upon reaching interrupt reference value. If IEN is set when WER[WIE] = 1, an immediate
interrupt occurs.
6.2.8.3 Watchdog Counter Register (WCR)
The WCR, Figure 6-10, contains the 16 most significant bits of the software watchdog counter. Writing
any value to WCR resets the counter and prescaler and should be executed on a regular basis if the
watchdog is enabled.
15
Field
Reset
0
COUNT
0000_0000_0000_0000
R/W
Address
R/W
MBAR + 0x288
Figure 6-10. Watchdog Counter Register (WCR)
6.2.8.4 Watchdog Event Register (WER)
The WER, Figure 6-11, reports when the watchdog timer reaches the WIRR value.
15
Field
Reset
R/W
Address
—
0000_0000_0000_0000
R/W
MBAR + 0x28C
Figure 6-11. Watchdog Event Register (WER)
1
0
WIE
Table 6-11 describes WER fields.
Table 6-11. WER Field Descriptions
Bits Field
Description
15–1
0
— Reserved, should be cleared.
WIE Watchdog interrupt event.
0 WIRR value has not been reached.
1 WIRR value has been reached.
WIE is cleared by writing a 1 to it. The timer does not negate the interrupt request to the interrupt controller until
WIE is cleared. WIE is set regardless of the state of WIRR[IEN]; however, an interrupt is not asserted to the
controller unless WIRR[IEN] = 1.
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
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