MCF5272VF66J Datasheet, PDF (348/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Queued Serial Peripheral Interface (QSPI) Module
Bits
13–10
9
8
7–0
Table 14-3. QMR Field Descriptions (continued)
Name
BITS
CPOL
CPHA
BAUD
Description
Transfer size. Determines the number of bits to be transferred for each entry in the queue.
Value Bits per transfer
0000 16
0001– 0111 Reserved
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
Clock polarity. Defines the clock polarity of SCK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK.
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.
Baud rate divider. The baud rate is selected by writing 0, or a value in the range 2–255. 1 is not a valid
value. A value of zero disables the QSPI. The desired QSPI_CLK baud rate is related to CLKIN and
QMR[BAUD] by the following expression:
QMR[BAUD] = SystemClock / [2 × (desired QSPI_CLK baud rate)]
Figure 14-4 shows an example of a QSPI clocking and data transfer.
QSPI_CLK
QSPI_Dout
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
msb
QSPI_Din
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A
B
QSPI_CS
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
Figure 14-4. QSPI Clocking and Data Transfer Example
14-10
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor