MSC8154E Datasheet, PDF (50/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor with Security

Electrical Characteristics
Table 36. SPI AC Timing Specifications
Parameter
Symbol ¹
Min
Max
Unit
Note
SPI inputs—Master mode (internal clock) input hold time
t_NIIXKH
0
—
ns
—
SPI inputs—Slave mode (external clock) input setup time
t_NEIVKH
4
—
ns
—
SPI inputs—Slave mode (external clock) input hold time
t_NEIXKH
2
—
ns
—
Notes: 1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)}
(reference)(state) ^{for inputs and t}(first two letters of functional block)(reference)(state)(signal)(state) ^{for outputs. For example,}
t_NIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until
outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal.
Timings are measured at the pin.
Figure 26 provides the AC test load for the SPI.
Output
Z₀ = 50 Ω
R_L = 50 Ω
V_DDIO/2
Figure 26. SPI AC Test Load
Figure 27 and Figure 28 represent the AC timings from Table 36. Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 27 shows the SPI timings in slave mode (external clock).
SPICLK (input)
Input Signals:
SPIMOSI
(See note)
Output Signals:
SPIMISO
(See note)
t_NEIVKH
t_NEIXKH
t_NEKHOV
Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0
Figure 27. SPI AC Timing in Slave Mode (External Clock)
Figure 28 shows the SPI timings in master mode (internal clock).
t_NEKHOX
SPICLK (output)
Input Signals:
SPIMISO
(See note)
Output Signals:
SPIMOSI
(See note)
t_NIIVKH
t_NIIXKH
t_NIKHOV
Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0
Figure 28. SPI AC Timing in Master Mode (Internal Clock)
t_NIKHOX
MSC8154E Quad-Core Digital Signal Processor with Security Data Sheet, Rev. 0
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Freescale Semiconductor