MSC8154E Datasheet, PDF (40/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor with Security

Electrical Characteristics
Figure 13 shows the DDR SDRAM output timing diagram.
MCK[n]
MCK[n]
t_MCK
ADDR/CMD
t_DDKHAS, t_DDKHCS
t_DDKHAX ,t_DDKHCX
Write A0
NOOP
t_DDKHMP
t_DDKHMH
MDQS[n]
MDQ[x]
D0
t_DDKHDX
t_DDKHDS
t_DDKLDS
D1
t_DDKLDX
Figure 13. DDR SDRAM Output Timing
Figure 14 provides the AC test load for the DDR2 and DDR3 controller bus.
Output
Z₀ = 50 Ω
R_L = 50 Ω
V_DDDDR/2
t_DDKHME
Figure 14. DDR2 and DDR3 Controller Bus AC Test Load
2.6.1.3 DDR2 and DDR3 SDRAM Differential Timing Specifications
This section describes the DC and AC differential timing specifications for the DDR2 and DDR3 SDRAM controller interface.
Figure 15 shows the differential timing specification.
GVDD
VTR
GV_DD/2
VCP
V_OX or V_IX
GND
Figure 15. DDR2 and DDR3 SDRAM Differential Timing Specifications
Note: VTR specifies the true input signal (such as MCK or MDQS) and VCP is the complementary input signal (such as
MCK or MDQS).
MSC8154E Quad-Core Digital Signal Processor with Security Data Sheet, Rev. 0
40
Freescale Semiconductor