MSC8154E Datasheet, PDF (27/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor with Security

Electrical Characteristics
2.5.1.2 DDR3 (1.5V) SDRAM DC Electrical Characteristics
Table 7 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM.
Note: At recommended operating conditions (see Table 3) with V_DDDDR = 1.5 V.
Table 7. DDR3 SDRAM Interface DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O reference voltage
MV_REF
0.49 × V_DDDDR
0.51 × V_DDDDR
V
2,3,4
Input high voltage
V_IH
MV_REF + 0.100
V_DDDDR
V
5
Input low voltage
V_IL
GND
MV_REF – 0.100
V
5
I/O leakage current
I_OZ
–50
50
μA
6
Notes: 1. V_DDDDR is expected to be within 50 mV of the DRAM V_DD at all times. The DRAM and memory controller can use the same or
different sources.
2. MV_REF is expected to be equal to 0.5 × V_DDDDR, and to track V_DDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MV_REF may not exceed ±1% of the DC value.
3. V_TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MV_REF with a minimum value of MV_REF – 0.4 and a maximum value of MV_REF + 0.04 V. V_TT should track variations
in the DC-level of MV_REF.
4. The voltage regulator for MV_REF must be able to supply up to 250 μA.
5. Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.
6. Output leakage is measured with all outputs are disabled, 0 V ≤ V_OUT ≤ V_DDDDR.
2.5.1.3 DDR2/DDR3 SDRAM Capacitance
Table 8 provides the DDR controller interface capacitance for DDR2 and DDR3 memory.
Note: At recommended operating conditions (see Table 3) with V_DDDDR = 1.8 V for DDR2 memory or V_DDDDR = 1.5 V for
DDR3 memory.
Table 8. DDR2/DDR3 SDRAM Capacitance
Parameter
Symbol
Min
Max
Unit
I/O capacitance: DQ, DQS, DQS
C_IO
6
8
pF
Delta I/O capacitance: DQ, DQS, DQS
C_DIO
—
0.5
pF
Notes: 1. This parameter is sampled. V_DDDDR = 1.8 V ± 0.1 V (for DDR2), f = 1 MHz, T_A = 25°C, V_OUT = V_DDDDR/2,
V_OUT (peak-to-peak) = 0.2 V.
2. This parameter is sampled. V_DDDDR = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, T_A = 25°C, V_OUT = V_DDDDR/2,
V_OUT (peak-to-peak) = 0.175 V.
Notes
1, 2
1, 2
MSC8154E Quad-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semiconductor
27