MSC8154E Datasheet, PDF (39/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor with Security

Electrical Characteristics
Table 21. DDR SDRAM Output AC Timing Specifications (continued)
Parameter
Symbol ¹
Min
Max
Unit Notes
Notes: 1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)} for
inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)} for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t_DDKHAS symbolizes DDR timing (DD) for the time t_MCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, t_DDKLDX symbolizes DDR timing (DD) for the time t_MCK memory clock reference (K)
goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t_DDKHMH follows the symbol conventions described in note 1. For example, t_DDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t_DDKHMH can be modified through control of
the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same
adjustment value. See the MSC8154E Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MSC8154E.
6. At recommended operating conditions with V_DDDDR (1.5 V or 1,8 V) ± 5%.
Note: For the ADDR/CMD setup and hold specifications in Table 21, it is assumed that the clock control register is set to
adjust the memory clocks by ½ applied cycle.
Figure 12 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t_DDKHMH).
MCK[n]
MCK[n]
t_MCK
t_{DDKHMHmax) = 0.6 ns or 0.375 ns}
MDQS
t_{DDKHMH(min) = –0.6 ns or –0.375 ns}
MDQS
Figure 12. MCK to MDQS Timing
MSC8154E Quad-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semiconductor
39