MSC8154E Datasheet, PDF (32/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor with Security

Electrical Characteristics
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to GND_SXC. Each signal wire of the differential inputs is allowed to
swing below and above the command mode voltage GND_SXC. Figure 8 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
200 mV < Input Amplitude or Differential Peak < 800 mV
SR[1–2]_REF_CLK
Vmax < Vcm + 400 mV
Vcm
SR[1–2]_REF_CLK
Vmin > Vcm – 400 mV
Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled)
• Single-Ended Mode
— The reference clock can also be single-ended. The SR[1–2]_REF_CLK input amplitude (single-ended swing)
must be between 400 mV and 800 mV peak-peak (from V_MIN to V_MAX) with SR[1–2]_REF_CLK either left
unconnected or tied to ground.
— The SR[1–2]_REF_CLK input average voltage must be between 200 and 400 mV. Figure 9 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SR[1–2]_REF_CLK) through the same source impedance as the clock input (SR[1–2]_REF_CLK) in use.
400 mV < SR[1–2]_REF_CLK Input Amplitude < 800 mV
SR[1–2]_REF_CLK
0V
SR[1–2]_REF_CLK
Figure 9. Single-Ended Reference Clock Input DC Requirements
2.5.3.2 DC-Level Requirements for PCI Express Configurations
The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The
MSC8154E supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The
transmitter specifications are defined in Table 11 and the receiver specifications are defined in Table 12.
MSC8154E Quad-Core Digital Signal Processor with Security Data Sheet, Rev. 0
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Freescale Semiconductor