MSC8154E Datasheet, PDF (48/68 Pages) Freescale Semiconductor, Inc – Quad-Core Digital Signal Processor with Security

Electrical Characteristics
2.6.5 Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8154E
Reference Manual.
2.6.5.1 Management Interface Timing
Table 33 lists the timer input Ethernet controller management interface timing specifications shown in Table 24.
Table 33. Ethernet Controller Management Interface Timing
Characteristics
Symbol
Min
Max
Unit
GE_MDC to GE_MDIO delay²
t_MDKHDX
10
70
ns
GE_MDIO to GE_MDC rising edge setup time
t_MDDVKH
7
—
ns
GE_MDC rising edge to GE_MDIO hold time
t_MDDXKH
0
—
ns
Notes: 1. Program the GE_MDC frequency (f_MDC) to a maximum value of 2.5 MHz (400 ns period for t_MDC). The value depends on the
source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz to
achieve f_MDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8154E Reference Manual for
configuration details.
2. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
t_MDC
GE_MDC
GE_MDIO
(Input)
GE_MDIO
(Output)
t_MDDVKH
t_MDDXKH
t_MDKHDX
Figure 24. MII Management Interface Timing
2.6.5.2 RGMII AC Timing Specifications
Table 34 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 34. RGMII at 1 GHz² with On-Board Delay³ AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max Unit
Data to clock output skew (at transmitter)⁴
Data to clock input skew (at receiver) ⁴
t_SKEWT
–-0.5
—
0.5
ns
t_SKEWR
1
—
2.6
ns
Notes: 1. At recommended operating conditions with V_DDIO of 2.5 V ± 5%.
2. RGMII at 100 MHz support is guaranteed by design.
3. Program GCR4 as 0x00000000.
4. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and
less than 2.0 ns is added to the associated clock signal.
MSC8154E Quad-Core Digital Signal Processor with Security Data Sheet, Rev. 0
48
Freescale Semiconductor