MC68332ACEH20 Datasheet, PDF (43/88 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
1. The dominant interrupt source supplies a vector number and DSACK signals appropriate
to the access. The CPU32 acquires the vector number.
2. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source
or the pin can be tied low), and the CPU32 generates an autovector number corresponding
to interrupt priority.
3. The bus monitor asserts BERR and the CPU32 generates the spurious interrupt vector
number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to
the exception handler routine.
3.9 Factory Test Block
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the
SIM to support production testing.
Test submodule registers are intended for Motorola use. Register names and addresses are provided
to indicate that these addresses are occupied.
SIMTR —System Integration Test Register
$YFFA02
SIMTRE —System Integration Test Register (E Clock)
$YFFA08
TSTMSRA —Master Shift Register A
$YFFA30
TSTMSRB —Master Shift Register B
$YFFA32
TSTSC —Test Module Shift Count
$YFFA34
TSTRC —Test Module Repetition Count
$YFFA36
CREG —Test Module Control Register
$YFFA38
DREG —Test Module Distributed Register
$YFFA3A
MC68332
MC68332TS/D
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MOTOROLA
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