MC68332ACEH20 Datasheet, PDF (28/88 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
3.4.8 Data Transfer Mechanism
The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit
data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge
inputs (DSACK1 and DSACK0).
3.4.9 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device sig-
nals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK0
and DSACK1 inputs, as shown in the following table.
DSACK1
1
1
0
0
Table 10 Effect of DSACK Signals
DSACK0
1
0
1
0
Result
Insert Wait States in Current Bus Cycle
Complete Cycle —Data Bus Port Size is 8 Bits
Complete Cycle —Data Bus Port Size is 16 Bits
Reserved
For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,
the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.
The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the
DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns
DSACK0 = 1 and DSACK1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word
operation.
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data
bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the
MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word oper-
ation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are desig-
nated as shown in the following figure. OP0 is the most significant byte of a long-word operand, and
OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and
OP1. The single byte of a byte-length operand is OP0.
Operand
Long Word
Three Byte
Word
Byte
31 24
OP0
Byte Order
23 16 15 8
OP1
OP2
OP0
OP1
OP0
Figure 8 Operand Byte Order
7
0
OP3
OP2
OP1
OP0
3.4.10 Operand Alignment
The data multiplexer establishes the necessary connections for different combinations of address and
data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required po-
sitions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the
remaining number of bytes to be transferred during the current bus cycle. The number of bytes trans-
ferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
MOTOROLA
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MC68332
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