MC68332ACEH20 Datasheet, PDF (35/88 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
DSACK — Data and Size Acknowledge
This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus
timing with internal DSACK generation by controlling the number of wait states that are inserted to op-
timize bus speed in a particular application. The following table shows the DSACK field encoding. The
fast termination encoding (1110) is used for two-cycle access to external memory.
DSACK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
No Wait States
1 Wait State
2 Wait States
3 Wait States
4 Wait States
5 Wait States
6 Wait States
7 Wait States
8 Wait States
9 Wait States
10 Wait States
11 Wait States
12 Wait States
13 Wait States
Fast Termination
External DSACK
SPACE — Address Space
Use this option field to select an address space for the chip-select logic. The CPU32 normally operates
in supervisor or user space, but interrupt acknowledge cycles must take place in CPU space.
Space Field
00
01
10
11
Address Space
CPU Space
User Space
Supervisor Space
Supervisor/User Space
IPL — Interrupt Priority Level
If the space field is set for CPU space (00), chip-select logic can be used for interrupt acknowledge.
During an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is compared to the
value in the IPL field. If the values are the same, a chip select is asserted, provided that other option
register conditions are met. The following table shows IPL field encoding.
IPL
Description
000
Any Level
001
IPL1
010
IPL2
011
IPL3
100
IPL4
101
IPL5
110
IPL6
111
IPL7
This field only affects the response of chip selects and does not affect interrupt recognition by the CPU.
Any level means that chip select is asserted regardless of the level of the interrupt acknowledge cycle.
MC68332
MC68332TS/D
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