MC68HC908AZ60A_13 Datasheet, PDF (347/414 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC MUX Interface
200 μs
128 μs
64 μs
ACTIVE
(1) INVALID ACTIVE BIT
PASSIVE
a
ACTIVE
(2) VALID ACTIVE LOGIC 1
PASSIVE
a
b
ACTIVE
(3) VALID ACTIVE LOGIC 0
PASSIVE
ACTIVE
b
c
(4) VALID SOF SYMBOL
PASSIVE
c
d
Figure 27-9. J1850 VPW Received Active Symbol Times
Valid Active Logic 1
In Figure 27-9 (2), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between a and b, the current bit would be considered a logic 1.
Valid Active Logic 0
In Figure 27-9 (3), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between b and c, the current bit would be considered a logic 0.
Valid SOF Symbol
In Figure 27-9 (4), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between c and d, the current symbol would be considered a valid SOF symbol.
Valid BREAK Symbol
In Figure 27-10, if the next active-to-passive received transition does not occur until after e, the current
symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be transmitted onto the J1850 bus. See
J1850 Frame Format for BDLC response to BREAK symbols.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
347