MC68HC908AZ60A_13 Datasheet, PDF (346/414 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
Valid Passive Logic 0
See Figure 27-7 (2). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between a and b, the current bit would be considered a logic 0.
Valid Passive Logic 1
See Figure 27-7 (3). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between b and c, the current bit would be considered a logic 1.
Valid EOD Symbol
See Figure 27-7 (4). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between c and d, the current symbol would be considered a valid end-of-data symbol (EOD).
300 μs
280 μs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(1) VALID EOF SYMBOL
a
b
(2) VALID EOF+
IFS SYMBOL
c
d
Figure 27-8. J1850 VPW Received Passive
EOF and IFS Symbol Times
Valid EOF and IFS Symbol
In Figure 27-8 (1), if the passive-to-active received transition beginning the SOF symbol of the next
message occurs between a and b, the current symbol will be considered a valid end-of-frame (EOF)
symbol.
See Figure 27-8 (2). If the passive-to-active received transition beginning the SOF symbol of the next
message occurs between c and d, the current symbol will be considered a valid EOF symbol followed
by a valid inter-frame separation symbol (IFS). All nodes must wait until a valid IFS symbol time has
expired before beginning transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others and immediately begin
transmitting. Therefore, any time a node waiting to transmit detects a passive-to-active transition once
a valid EOF has been detected, it should immediately begin transmission, initiating the arbitration
process.
Idle Bus
In Figure 27-8 (2), if the passive-to-active received transition beginning the start-of-frame (SOF)
symbol of the next message does not occur before d, the bus is considered to be idle, and any node
wishing to transmit a message may do so immediately.
Invalid Active Bit
In Figure 27-9 (1), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between the passive-to-active transition beginning the current data bit (or symbol) and a, the
current bit would be invalid.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
346
Freescale Semiconductor