MC68HC908AZ60A_13 Datasheet, PDF (182/414 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface (SCI)
Register Name
Bit 7
6
5
4
3
2
1
Read: SCTE
TC
SCRF
IDLE
OR
NF
FE
SCI Status Register 1 (SCS1) Write:
Reset: 1
1
0
0
0
0
0
Read: R7
R6
R5
R4
R3
R2
R1
SCI Data Register (SCDR) Write: T7
T6
T5
T4
T3
T2
T1
Reset:
Unaffected by Reset
Read: 0
SCI Baud Rate Register (SCBR) Write:
0
SCP1
SCP0
R
SCR2
SCR1
Reset: 0
0
0
0
0
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 18-5. SCI Transmitter I/O Register Summary (Continued)
Bit 0
PE
0
R0
T0
SCR0
0
Table 18-3. SCI Transmitter I/O Address Summary
Register
Address
SCC1
$0013
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCDR
$0018
SCBR
$0019
18.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break
character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character
length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads
break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one 1. The automatic 1 at the end of a
break character guarantees the recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be. Receiving a break character has the following effects on SCI
registers:
• Sets the framing error bit (FE) in SCS1
• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
182
Freescale Semiconductor