MC68HC908AZ60A_13 Datasheet, PDF (264/414 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Ports
DDRG[2:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins
as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 22-22 shows the port G I/O logic.
READ DDRG ($000E)
WRITE DDRG ($000E)
RESET
WRITE PTG ($000A)
DDRGx
PTGx
PTGx
READ PTG ($000A)
Figure 22-22. Port G I/O Circuit
When bit DDRGx is a logic 1, reading address $000A reads the PTGx data latch. When bit DDRGx is a
logic 0, reading address $000A reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-7 summarizes the operation of the port G pins.
Table 22-7. Port G Pin Functions
DDRG
Bit
PTG
Bit
I/O Pin
Mode
Accesses to DDRG
Read/Write
0
X
Input, Hi-Z
DDRG[2:0]
1
X
Output
DDRG[2:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Accesses to PTG
Read
Write
Pin
PTG[2:0]⁽¹⁾
PTG[2:0]
PTG[2:0]
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
264
Freescale Semiconductor