33892 Datasheet, PDF (3/28 Pages) Freescale Semiconductor, Inc – Quad Intelligent High-Side Switch

Freescale Semiconductor, Inc.
Transparent Top View of Package
V_DD 11
SO 12
GND 13
14
HS3
10 9 8 7 6 5 4 3 2 1
GND
15
24 _IN0
23 CSNS
22 FSI
21
HS2
16
V_PWR
HS1 ₁₇
TERMINAL FUNCTION DESCRIPTION
Terminal Terminal Name
Formal Name
1
IN1
2
IN2
3
IN3
24
IN0
Serial Inputs
4
FS
Fault Status
(Active Low)
5
WAKE
Wake
6, 13, 15
7
GND
RST
Ground
Reset
8
CS
Chip Select
(Active Low)
9
SCLK
Serial Clock
18
19
20 ^HS0
HS1
HS0
Definition
The IN0–IN3 high-side input terminals are used to directly control HS0–HS3 high-side
output terminals, respectively. An SPI register determines if each input is activated or
if the input logic state is ORed or ANDed with the SPI instruction. These terminals are
to be driven with 5.0 V CMOS levels, and they have an internal active pull-down current
source.
This terminal is an open drain configured output requiring an external pull-up resistor
to V_DD for fault reporting. If a device fault condition is detected, this terminal is active
LOW. Specific device diagnostic faults are reported via the SPI SO terminal.
This terminal is an input that controls the device mode and watchdog timeout feature
if enabled. An internal clamp protects this terminal from high damaging voltages when
the output is current limited with an external resistor. This input has an internal passive
pull-down.
These terminals are the ground for the logic and analog circuitry of the device.
This terminal is an input used to initialize the device configuration and fault registers,
as well as place the device in a low-current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not
be allowed to be logic [1] until V_DD is in regulation. This terminal has an internal passive
pull-down.
This terminal is an input terminal connected to a chip select output of a master
microcontroller (MCU). The MCU determines which device is addressed (selected) to
receive data by pulling the CS terminal of the selected device logic LOW, thereby
enabling SPI communication with the device. Other unselected devices on the serial
link having their CS terminals pulled up logic HIGH disregard the SPI communication
data sent. This terminal has an internal active pull-up current source and requires
CMOS logic levels.
This terminal is an input terminal connected to the MCU providing the required bit shift
clock for SPI communication. It transitions one time per bit transferred at an operating
frequency, f_SPI, defined by the communication interface. The 50 percent duty cycle
CMOS level serial clock signal is idle between command transfers. The signal is used
to shift data into and out-of the device. This terminal has an internal active pull-down.
MOTOROLA ANALOG INTEGRATED CIR_FC_oU_rIT_MDE_oV_rI_eCE_ID_nA_foTA_{rmation On This Product,}
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33892
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