33892 Datasheet, PDF (17/28 Pages) Freescale Semiconductor, Inc – Quad Intelligent High-Side Switch

Freescale Semiconductor, Inc.
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33892 is one in a family of devices designed for low-
voltage automotive and industrial lighting and motor control
applications. Its four low R_DS(ON) MOSFETs (two 10 mΩ, two
35 mΩ) can control the high sides of four separate resistive or
inductive loads or serve as high-side switches for a pair of DC
motors.
Programming, control, and diagnostics are accomplished
using a 16-bit SPI interface. Additionally, each output has its
own parallel input for PWM control if desired. The 33892 allows
the user to program via the SPI the fault current trip levels and
duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can
protect wiring harnesses and circuit boards as well as loads.
The 33892 is packaged in a power-enhanced 10 x 10 PQFN
package with exposed tabs.
FUNCTIONAL DESCRIPTION
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Input
(SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select
(CS).
The SI/SO terminals of the 33892 follow a first-in first-out
(D15 to D0) protocol, with both input and output words
transferring the most significant bit (MSB) first. All inputs are
compatible with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
Serial Input (SI)
This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The internal registers of the 33892 are configured and
controlled using a 5-bit addressing scheme described in
Table 1, page 18. Register addressing and configuration are
described in Table 2, page 19. The SI input has an internal pull-
down, I_DWN.
Serial Output (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes state on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and input status descriptions are
provided in Table 9, page 22.
Serial Clock (SCLK)
The SCLK terminal clocks the internal shift registers of the
33892 device. The serial input (SI) terminal accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) terminal shifts data information out
of the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK terminal be in a logic low state whenever
CS makes any transition. For this reason, it is recommended the
SCLK terminal be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an internal pull-down.
When CS is logic [1], signals at the SCLK and SI terminals are
ignored and SO is tri-stated (high impedance) (see Figure 7,
page 18).
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33892 latches in data
from the Input Shift registers to the addressed registers on the
rising edge of CS. The 33892 transfers status information from
the power output to the Shift register on the falling edge of CS.
The SO output driver is enabled when CS is logic [0]. CS should
transition from a logic [1] to a logic [0] state only when SCLK is
a logic [0]. CS has an internal pull-up, I_UP.
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33892
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