33892 Datasheet, PDF (13/28 Pages) Freescale Semiconductor, Inc – Quad Intelligent High-Side Switch

Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ V_DD ≤ 5.5 V, 6.0 V ≤ V_PWR ≤ 27 V, -40°C ≤ T_J ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
f_SPI
–
Required Low State Duration for RST (Note 29)
t_WRST
–
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 30)
t_CS
–
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 30) t_ENBL
–
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 30) t_LEAD
–
Required High State Duration of SCLK (Required Setup Time) (Note 30)
t_WSCLKh
–
Required Low State Duration of SCLK (Required Setup Time) (Note 30)
t_WSCLKl
–
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 30)
t_LAG
–
SI to Falling Edge of SCLK (Required Setup Time) (Note 31)
t_{SI (SU)}
–
Falling Edge of SCLK to SI (Required Setup Time) (Note 31)
t_{SI (HOLD)}
–
SO Rise Time
C_L = 200 pF
t_RSO
–
–
3.0
MHz
50
350
ns
–
300
ns
–
5.0
µs
50
167
ns
–
167
ns
–
167
ns
50
167
ns
25
83
ns
25
83
ns
ns
25
50
SO Fall Time
C_L = 200 pF
t_FSO
–
ns
25
50
SI, CS, SCLK, Incoming Signal Rise Time (Note 31)
SI, CS, SCLK, Incoming Signal Fall Time (Note 31)
Time from Falling Edge of CS to SO Low Impedance (Note 32)
Time from Rising Edge of CS to SO High Impedance (Note 33)
Time from Rising Edge of SCLK to SO Data Valid (Note 34)
0.2 V_DD ≤ SO ≥ 0.8 V_DD, C_L = 200 pF
t_RSI
–
t_FSI
–
t_SO(EN)
–
t_SO(DIS)
–
t_VALID
–
–
50
ns
–
50
ns
–
145
ns
65
145
ns
ns
65
105
Notes
29. RST low duration measured with outputs enabled and going to OFF or disabled condition.
30. Maximum setup time required for the 33892 is the minimum guaranteed time needed from the microcontroller.
31. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
32. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
33. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
34. Time required to obtain valid data out from SO following the rise of SCLK.
MOTOROLA ANALOG INTEGRATED CIR_FC_oU_rIT_MDE_oV_rI_eCE_ID_nA_foTA_{rmation On This Product,}
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33892
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