33892 Datasheet, PDF (20/28 Pages) Freescale Semiconductor, Inc – Quad Intelligent High-Side Switch

Freescale Semiconductor, Inc.
Table 4. Overcurrent Low Detection Levels
SOCL2_s*
(D2)
SOCL1_s*
(D1)
SOCL0_s*
(D0)
Overcurrent Low
Detection (Amperes)
HS0 or HS1 HS2 or HS3
0
0
0
18.2
9.1
0
0
1
16.3
8.15
0
1
0
14.4
7.2
0
1
1
12.5
6.25
1
0
0
10.5
5.25
1
0
1
8.6
4.3
1
1
0
6.7
3.35
1
1
1
4.8
2.4
* “_s” refers to the channel, which is selected through bits D12–D11;
refer to Table 3, page 19.
Table 5. Overcurrent High Detection
Levels
SOCH_s* (D3)
Overcurrent High Detection
(Amperes)
HS0 or HS1 HS2 or HS3
0
100
50
1
70
35
* “_s” refers to the channel, which is selected
through bits D12–D11; refer to Table 3, page 19.
Address A₁A₀011—Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine the
amount of time the 33892 will allow an overcurrent low condition
before an output latches OFF. Each output is independently
selected for configuration based on A₁A₀, which are the state of
the D12–D11 bits (refer to Table 3, page 19).
Bits D1–D0 (OCLT[1:0]_s) allow the MCU to select one of
four overcurrent fault blanking times defined in Table 6. Note
that these timeouts apply only to the overcurrent low detection
levels. If the selected overcurrent high level is reached, the
device will latch off within 20 µs.
Table 6. Overcurrent Low Detection
Blanking Time
OCLT[1:0]_s*
Timing
00
155 ms
01
620 ms
10
75 ms
11
150 µs
* “_s” refers to the channel, which is selected through
bits D12–D11; refer to Table 3, page 19.
A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent
low detection feature. When disabled, there is no timeout for the
selected output and the overcurrent low detection feature is
disabled.
A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL)
detection feature for the channel corresponding to the state of
bits D12–D11.
Address A₁A₀100—Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of each output. Each
output is independently selected for configuration based on the
state bits D12–D11 (refer to Table 3, page 19).
For the selected output, a logic [0] on bit D1 (DIR_DIS_s) will
enable the output for direct control. A logic [1] on bit D1 will
disable the output from direct control.
While addressing this register, if the Input was enabled for
direct control, a logic [1] for the D0 (A/O_s) bit will result in a
Boolean AND of the IN terminal with its corresponding IN_SPI
D[4:0] message bit when addressing OCR0. Similarly, a logic
[0] on the D0 terminal results in a Boolean OR of the IN terminal
to the corresponding message bits when addressing the OCR0.
This register is especially useful if several loads are required to
be independently PWM controlled. For example, the IN
terminals of several devices can be configured to operate all of
the outputs with one PWM output from the MCU. If each output
is then configured to be Boolean ANDed to its respective IN
terminal, each output can be individually turned OFF by SPI
while controlling all of the outputs, commanded on with the
single PWM output.
A logic [1] on bit D2 (CSNS_high_s) is used to select the
high ratio on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (Table 7).
Table 7. Current Sense Ratio
CSNS_high_s* (D2)
Current Sense Ratio
HS0 or HS1 HS2 or HS3
0
1/13000
1/6500
1
1/40000
1/20000
* “_s” refers to the channel, which is selected through
bits D12–D11; refer to Table 3, page 19.
A logic [1] on bit D3 (FAST_SR_s) is used to select the high
speed slew rate for the selected output, the default value [0]
corresponds to the low speed slew rate
Address x0101—Undervoltage/Overvoltage Register
(UOVR)
The UOVR register disables the undervoltage (D1) and/or
overvoltage (D0) protection. When these two bits are [0], the
under- and overvoltage are active (default value).
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