33892 Datasheet, PDF (21/28 Pages) Freescale Semiconductor, Inc – Quad Intelligent High-Side Switch

Freescale Semiconductor, Inc.
Address x1101— Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
Watchdog timeout. The Watchdog timeout is configured using
bits D1 and D0. When D1 and D0 bits are programmed for the
desired watchdog timeout period (Table 8), the WDSPI bit
should be toggled as well, ensuring the new timeout period is
programmed at the beginning of a new count sequence.
Table 8. Watchdog Timeout
WD[1:0] (D1, D0)
Timing (ms)
00
620
01
310
10
2500
11
1250
Address xx110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy-chain SPI configuration. This would allow
devices to be unaffected by commands being clocked over a
daisy-chained SPI configuration. By toggling the WD bit (D15)
the watchdog circuitry would continue to be reset while no
programming or data read back functions are being requested
from the device.
Address xx111—TEST
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
Serial Output Communication (Device Status Return
Data)
When the CS terminal is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-) first
as the new message data is clocked into the SI terminal. The
first sixteen bits of data clocking out of the SO, and following a
CS transition, is dependent upon the previously written SPI
word.
Any bits clocked out of the Serial Output (SO) terminal after
the first 16 bits will be representative of the initial message bits
clocked into the SI terminal since the CS terminal first
transitioned to a logic [0]. This feature is useful for daisy
chaining devices as well as message verification.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the data
is latched into the appropriate registers. A valid message length
is a multiple of 16 bits. At this time, the SO terminal is tri-stated
and the fault status register is now able to accept new fault
status information.
SO data will represent information ranging from fault status
to register contents, user selected by writing to the STATR bits
OD4, OD3, OD2, OD1, and OD0. The value of the previous bits
SOA4 and SOA3 will determine which output the SO
information applies to for the registers which are output specific;
viz., Fault, SOCHLR, CDTOLR, and DICR registers.
Note that the SO data will continue to reflect the information
for each output (depending on the previous OD4, OD3 state)
that was selected during the most recent STATR write until
changed with an updated STATR write.
The output status register correctly reflects the status of the
STATR-selected register data at the time that the CS is pulled
to a logic [0] during SPI communication, and/or for the period of
time since the last valid SPI communication, with the following
exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage V_PWR condition should be
ignored.
• The RST terminal transition from a logic [0] to [1] while the
WAKE terminal is at logic [0] may result in incorrect data
loaded into the Status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
Serial Output Bit Assignment
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following paragraphs.
Table 9, page 22, summarizes SO returned data for bits OD15
through OD0.
• Bit OD15 is the MSB; it reflects the state of the Watchdog
bit from the previously clocked-in message.
• Bit OD14 remains logic [0] except when an undervoltage
condition occurred.
• Bit OD13 remains logic [0] except when an overvoltage
condition occurred.
• Bits OD[12:8] reflect the state of the bits SOA[4:0] from the
previously clocked in message.
• Bits OD[7:4] give the fault status flag of the outputs HS3,
HS2, HS1, and HS0, respectively.
• The contents of bits OD[3:0] depend on bits D[4:0] from
the most recent STATR command SOA[4:0] as explained
in the paragraphs following the table.
MOTOROLA ANALOG INTEGRATED CIR_FC_oU_rIT_MDE_oV_rI_eCE_ID_nA_foTA_{rmation On This Product,}
Go to: www.freescale.com
33892
21