33892 Datasheet, PDF (18/28 Pages) Freescale Semiconductor, Inc – Quad Intelligent High-Side Switch

Freescale Semiconductor, Inc.
CCSSB
CS
SCLK
SI
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
NOTE^NS^o: ^t1^e.^s
2.
3.
1. RST is a logic [1] state during the above operation.
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Figure 7. Single 16-Bit Word SPI Communication
Serial Input Communication
SPI communication is accomplished using 16-bit messages.
A message is transmitted by the MCU starting with the MSB
D15 and ending with the LSB, D0 (Table 1). Each incoming
command message on the SI terminal can be interpreted using
the following bit assignments: the MSB, D15, is the watchdog
bit. In some cases, output channel selection is done with bits
D12–D11. The next three bits, D10–D8, are used to select the
command register. The remaining five bits, D4–D0, are used to
configure and control the outputs and their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to latch
in a message that is not 16 bits will be ignored.
The 33892 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 2, page 19, summarizes the SI registers.
Table 1. SI Message Bit Assignment
Bit Sig SI Msg Bit
Message Bit Description
MSB
D15 Watchdog in: toggled to satisfy watchdog
requirements.
D14–D15 Not used.
D12–D11 Register address bits used in some cases for
output channel selection.
D10–D8 Register address bits.
D7 –D5
D4 – D1
Not used.
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
LSB
D0
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
33892
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