K20P121M100SF2 Datasheet, PDF (22/68 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 11. JTAG limited voltage range electricals (continued)
Symbol
J2
J3
Description
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
1/J1
50
20
10
Max.
—
—
—
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
J6
Boundary scan input data hold time after TCLK rise
J7
TCLK low to boundary scan output data valid
J8
TCLK low to boundary scan output high-Z
J9
TMS, TDI input data setup time to TCLK rise
J10
TMS, TDI input data hold time after TCLK rise
J11
TCLK low to TDO data valid
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
3
20
—
0
—
—
25
—
25
8
—
1
—
—
17
—
17
100
—
8
—
Symbol
J1
J2
J3
J4
J5
J6
J7
J8
Table 12. JTAG full voltage range electricals
Description
Operating voltage
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
1.71
0
0
0
TCLK cycle period
1/J1
TCLK clock pulse width
• Boundary Scan
50
• JTAG and CJTAG
25
• Serial Wire Debug
12.5
TCLK rise and fall times
—
Boundary scan input data setup time to TCLK rise
20
Boundary scan input data hold time after TCLK rise
0
TCLK low to boundary scan output data valid
—
TCLK low to boundary scan output high-Z
—
Table continues on the next page...
Max.
3.6
10
20
40
—
—
—
3
—
—
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
22
Preliminary
Freescale Semiconductor, Inc.