XPC8260ZUHFBC Datasheet, PDF (20/41 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
3 Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 12 shows the eight basic configuration
modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins
on the data bus.
NOTE
Clock configurations change only after POR is asserted.
3.1 Local Bus Mode
Table 12 describes default clock modes for the MPC8260.
Table 12. Clock Default Modes
MODCK[1–3]
000
001
010
011
100
101
110
111
Input Clock
Frequency
33 MHz
33 MHz
33 MHz
33 MHz
66 MHz
66 MHz
66 MHz
66 MHz
CPM Multiplication
Factor
3
3
4
4
2
2
2.5
2.5
CPM
Frequency
Core Multiplication Factor Core Frequency
100 MHz
4
133 MHz
100 MHz
5
166 MHz
133 MHz
4
133 MHz
133 MHz
5
166 MHz
133 MHz
2.5
166 MHz
133 MHz
3
200 MHz
166 MHz
2.5
166 MHz
166 MHz
3
200 MHz
Table 13 describes all possible clock configurations when using the hard reset configuration sequence.
Note also that basic modes are shown in boldface type.
Table 13. Clock Configuration Modes¹
MODCK_H–MODCK[1–3]
Input Clock
Frequency^2,3,4
0001_000
0001_001
0001_010
0001_011
0001_100
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
CPM Multiplication
Factor^{2, 5}
2
2
2
2
2
CPM
Core Multiplication
Frequency²
Factor^{2, 6}
66 MHz
4
66 MHz
5
66 MHz
6
66 MHz
7
66 MHz
8
Core
Frequency²
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
20
Freescale Semiconductor