XPC8260ZUHFBC Datasheet, PDF (19/41 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Figure 11 shows signal behavior in MEMC mode.
CLKin
Electrical and Thermal Characteristics
V_CLK
Memory controller signals
sp34/sp30
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC8260 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is divided
by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and
T4 depends on the PLL clock ratio selected, as shown in Table 11.
Table 11. Tick Spacing for Memory Controller Signals
PLL Clock Ratio
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6 1/4 CLKin
1:2.5
3/10 CLKin
1:3.5
4/14 CLKin
1/2 CLKin
1/2 CLKin
1/2 CLKin
3/4 CLKin
8/10 CLKin
11/14 CLKin
Figure 12 is a graphical representation of Table 11.
CLKin
T1
T2
T3
T4
for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin
T1
T2
T3
T4
for 1:2.5
CLKin
for 1:3.5
T1
T2
T3
T4
Figure 12. Internal Tick Spacing for Memory Controller Signals
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
19