XPC8260ZUHFBC Datasheet, PDF (2/41 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Features
Figure 1 shows the block diagram for the MPC8260.
G2 Core
16 Kbytes
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
Interrupt
Controller
24 Kbytes
Dual-Port RAM
32-bit RISC Microcontroller
and Program ROM
Serial
DMAs
2 Virtual
IDMAs
System Interface Unit
(SIU)
Bus Interface Unit
60x-to-Local
Bridge
Memory Controller
Clock Counter
System Functions
60x Bus
Local Bus
32 bits, up to 66 MHz
MCC1¹ MCC2 FCC1 FCC2 FCC3¹ SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI
I²C
Time Slot Assigner
Serial Interface
8 TDM Ports²
Notes:
1 _{Not on MPC8255}
2 _{4 on the MPC8255}
3 _{2 on the MPC8255}
3 MII
Ports³
2 UTOPIA
Ports
Non-Multiplexed
I/O
Figure 1. MPC8260 Block Diagram
1 Features
The major features of the MPC8260 are as follows:
• Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 133–200 MHz (150–200 MHz for the
MPC8255)
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
2
Freescale Semiconductor