XPC8260ZUHFBC Datasheet, PDF (17/41 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
Table 10. AC Characteristics for SIU Outputs¹
Spec Number
Max
Min
Characteristic
Max Delay (ns) Min Delay (ns)
66 MHz
66 MHz
sp31
sp30 PSDVAL/TEA/TA
10
0.5
sp32
sp30 ADD/ADD_atr./BADDR/CI/GBL/WT
8
0.5
sp33a
sp30 Data bus
8
0.5
sp33b
sp30 DP
12
0.5
sp34
sp30 memc signals/ALE
6
0.5
sp35
sp30 all other signals
7.5
0.5
Note:
1 _{Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are}
measured at the pin.
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
Figure 8 shows TDM input and output signals.
Serial CLKin
TDM input signals
TDM output signals
sp20
sp21
sp40/sp41
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 8. TDM Signal Diagram
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
17