MC9S12DT128_1002 Datasheet, PDF (127/140 Pages) Freescale Semiconductor, Inc – Device User Guide

A.7 SPI
Device User Guide — 9S12DT128DGV2/D V02.17
A.7.1 Master Mode
Figure A-6 and Figure A-7 illustrate the master mode timing. Timing values are shown in (Table
A-18).
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
2
1
4
4
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
5
6
MSB IN²
BIT 6 . . . 1
MOSI
(OUTPUT)
9
MSB OUT²
9
BIT 6 . . . 1
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
11
3
12
LSB IN
10
LSB OUT
Figure A-6 SPI Master Timing (CPHA = 0)
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