MC9S12DT128_1002 Datasheet, PDF (120/140 Pages) Freescale Semiconductor, Inc – Device User Guide

Device User Guide — 9S12DT128DGV2/D V02.17
C_p
VDDPLL
C_s
R
Phase
XFC Pin
VCO
f_osc
1
f_ref
refdv+1
∆
K_Φ
K_V
f_vco
Detector
f_cmp
Loop Divider
1
1
synr+1
2
Figure A-3 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K₁, f₁ and i_ch from (Table A-16).
The grey boxes show the calculation for f_VCO = 50MHz and f_ref = 1MHz. E.g., these frequencies are used
for f_OSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
K_V = K₁ ⋅ e^{-(--fK--1--1--–--⋅--f-1-v--c-V--o}₌^---) _{–100 ⋅ e}^{(---6---–0---1--–--0---50---0--}₌^--) _-90.48MHz/V
The phase detector relationship is given by:
K_Φ = – i_ch ⋅ K_V
= 316.7Hz/Ω
i_ch is the current in tracking mode.
The loop bandwidth f_C should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
f_C < ----------2-----^â‹---^ζ----^â‹---f--^r--^e---^f----------
π ⋅ _{ζ} + 1 + ζ²_
1--1--0-- ^{→ fC <} 4----f-⋅^{r--e-1---f-0- ;(ζ}
f_C < 25kHz
= 0.9)
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