MC9S12DT128_1002 Datasheet, PDF (119/140 Pages) Freescale Semiconductor, Inc – Device User Guide

Device User Guide — 9S12DT128DGV2/D V02.17
Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert
Frequency f_CMFA.
Table A-15 Oscillator Characteristics
Conditions are shown in (Table A-4) unless otherwise noted
Num C
Rating
Symbol
Min
1a C Crystal oscillator range (Colpitts)
f_OSC
0.5
1b C _{Crystal oscillator range (Pierce)} ¹
f_OSC
0.5
2 P Startup Current
i_OSC
100
3 C Oscillator start-up time (Colpitts)
t_UPOSC
4 D Clock Quality check time-out
t_CQOUT
0.45
5 P Clock Monitor Failure Assert Frequency
f_CMFA
50
6 P _{External square wave input frequency} ⁴
f_EXT
0.5
7 D External square wave pulse width low
8 D External square wave pulse width high
t_EXTL
9.5
t_EXTH
9.5
9 D External square wave rise time
t_EXTR
10 D External square wave fall time
t_EXTF
11 D Input Capacitance (EXTAL, XTAL pins)
C_IN
12
C
DC Operating Bias in Colpitts Configuration on
EXTAL Pin
V_DCBIAS
13 P _{EXTAL Pin Input High Voltage}⁴
V_IH,EXTAL 0.75*V_DDPLL
T _{EXTAL Pin Input High Voltage}⁴
V_IH,EXTAL
14 P _{EXTAL Pin Input Low Voltage}⁴
V_IL,EXTAL
T _{EXTAL Pin Input Low Voltage}⁴
V_IL,EXTAL V_SSPLL - 0.3
15 C _{EXTAL Pin Input Hysteresis}⁴
V_HYS,EXTAL
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. f_osc = 4MHz, C = 22pF.
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. XCLKS =0 during reset
Typ
8²
100
7
1.1
250
Max
16
40
100³
2.5
200
50
1
1
Unit
MHz
MHz
µA
ms
s
KHz
MHz
ns
ns
ns
ns
pF
V
V
V_DDPLL + 0.3 V
0.25*V_DDPLL V
V
mV
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Freescale Semiconductor
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