AK4115-A Datasheet, PDF (9/32 Pages) Asahi Kasei Microsystems – Evaluation Board Rev.3

ASAHI KASEI
[AKD4115-A]
d. Set-up of PSEL, CM1 and CM0
d-1. In case of synchronous mode.
Please refer to Table 8.
d-2. In case of asynchronous mode
CM1
bit
0
0
1
1
CM0
(UNLOCK) PLL
X'tal
bit
Clock
source
RX
Clock
I/O
SDTO
Clock
source
Clock
I/O
X’tal or
0
-
PLL
ON ON(Note 2)
Note 3
RX
EMCK Note 4 Default
(RX)
(Note 5)
X’tal or
1
-
OFF
ON
X’tal Note 3 “L”
Note 4
EMCK
PLL
X’tal or
0
ON
ON
Note 3
RX
Note 4
(RX)
EMCK
0
X’tal or
1
ON
ON
X’tal Note 3 “L”
Note 4
EMCK
X’tal or
1
-
ON
ON
X’tal Note 3 “L”
Note 4
EMCK
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note 2: When the X’tal is not used as clock comparison for sampling frequency detection (i.e. XTL1, 0 =
“1, 1”), the X’tal is OFF.
Note 3: MCKO1/2, BICK, LRCK
Note 4: EMCK OR X’tal, EBICK, ELRCK, DAUX
Note 5: When X’tal is OFF, the clock source supports EMCK only.
Table 21. Clock Operation Mode Select
<KM076403>
-9-
2006/08