AK4115-A Datasheet, PDF (5/32 Pages) Asahi Kasei Microsystems – Evaluation Board Rev.3

ASAHI KASEI
[AKD4115-A]
d. Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_4, SW3_1
and JP18. In serial mode, it can be selected by PSEL bit and CM1-0 bits.
PSEL pin CM1 pin CM0 pin
SDTO
(SW3_4) (SW3_1) (JP18) (UNLOCK) PLL
X'tal
Clock source
source
PSEL bit CM1 bit CM0 bit
0
0
0
-
ON ON(Note) PLL(RX)
RX
0
0
1
-
OFF
ON
X'tal
DAUX
0
1
0
0
ON
ON
PLL(RX)
RX
1
ON
ON
X'tal
DAUX
0
1
1
-
ON
ON
X'tal
DAUX
1
0
0
-
ON ON(Note) PLL(ELRCK) DAUX
1
0
1
-
OFF
ON
X'tal
DAUX
1
1
0
0
ON
ON
PLL(ELRCK) DAUX
1
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 8. Clock Operation Mode Select
Default
<KM076403>
-5-
2006/08