AK4115-A Datasheet, PDF (7/32 Pages) Asahi Kasei Microsystems – Evaluation Board Rev.3

ASAHI KASEI
[AKD4115-A]
b. Set-up of clock input and output
b-1. In the case of synchronous mode (ASYNC bit="0" or Parallel mode)
The used signals are MCKO1, MCKO2, LRCK, BICK, ELRCK and DAUX.
The signal level outputted and inputted from PORT2 and PORT5 is 3.3V.
Clock
PORT
MCLK
PORT2
BICK
PORT2
LRCK
PORT2
DAUX
PORT5
ELRCK
PORT5(LRCK)
Table 11. Clock input and output
b-1-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2
sets up by OCKS 1-0.
Output
signal
JP12
JP15
JP11
MCKO1 MCKO1
MCKO
MCKO1
MCKO2 MCKO2
MCKO
MCKO2
Table 12. Selection of MCKO1/MCKO2
Default
OCKS1 pin
(SW3_2)
OCKS1 bit
0
0
1
1
OCKS0 pin
(SW3_3)
OCKS0 bit
(X’tal)
MCKO1 MCKO2
0
256fs
256fs
256fs
1
256fs
256fs
128fs
0
512fs
512fs
256fs
1
128fs
128fs
64fs
Table 13. Master Clock Frequency Select
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Default
b-1-2. Set-up of BICK and LRCK input and output
Please select SW 3_7 (DIR_I/O) according the setup of audio format of AK4115 (Refer to Table 7).
Audio format
SW3_7 (DIR_I/O)
Slave mode
0
Master mode
1
Table 14. Set-up DIR_I/O
Default
b-1-3. A set up of ELRCK
As a reference clock of PLL, when using ELRCK clock, it inputs from PORT5 (LRCK).
JP16
When inputting by AC coupling
AC
When inputting by CMOS level
DC
Table 15. Set-up of ELRCK input
JP17
AC
DC
Default
<KM076403>
-7-
2006/08