AK4115-A Datasheet, PDF (3/32 Pages) Asahi Kasei Microsystems – Evaluation Board Rev.3

ASAHI KASEI
a-3. Set-up of AK4115 input path
In Parallel Mode you will need to use SW1_1 & SW1_5.
In Serial Mode you will need to use IPS2-0 bits.
-
IPS1 pin IPS0 pin
(SW1_5) (SW1_1)
INPUT Data
IPS2 bit IPS1 bit IPS0 bit
0
0
0
RX0
0
0
1
RX1
0
1
0
RX2
0
1
1
RX3
1
0
0
RX4
1
0
1
RX5
1
1
0
RX6
1
1
1
RX7
(In parallel mode, IPS2 is fixed to “0”)
Table 3. Recovery Data Select
Default
b. Set-up of clock input and output
The signal level outputted/inputted from PORT2 is 3.3V.
PORT2
DIR
1
5
[AKD4115-A]
10
6
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2
is selected by OCKS 1-0.
Output
signal
JP12
MCKO1 MCKO1 Default
MCKO2 MCKO2
Table 4. MCKO1/MCKO2 set-up
OCKS1 pin
(SW3_2)
OCKS1 bit
0
0
1
1
OCKS0 pin
(SW3_3)
OCKS0 bit
(X’tal)
MCKO1 MCKO2
0
256fs
256fs
256fs
1
256fs
256fs
128fs
0
512fs
512fs
256fs
1
128fs
128fs
64fs
Table 5. Master Clock Frequency Select
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Default
<KM076403>
-3-
2006/08